Timing-module: introduction

A previous section about the CPU's dynamic behaviour already explained how the incoming clock-signal is divided into 4 "phase"-signals.

Each of these signals emit a pulse in turn. Each pulse activates specific subsystem(s) in turn, so that everything inside the CPU happens when it should.

The section about dynamic behaviour showed what happened on each such phase-pulse in terms of subsystem-activity.

The current section explains how these phase-pulses are formed out of the incoming clock-signal.

Disclaimer

Althought the steps in going from external clock-signal to phase-pulses are discussed, the actual logic performing these steps is left out.

The reason for this is that the timing-module is being enhanced at this moment, so the actual implementation-details are not yet clear.

Generating clock-edge pulses Pr and Pf

As mentioned in the previous section about the CPU's dynamic behaviour, the input-clock can be considered a square wave with equal high- and low-times.

Using 2 edge-detector circuits, fixed-length pulses can be generated at the rising and falling edges of the clock-signal, as shown here as Pr and Pf respectively.

(The lengths of Pr and Pf are not related to the high- or low-times of the input-clock, but are a direct result of the component-values within the edge-detector circuits.)

Each of these pulses should be shorter than the high- respectively low-time of the original clock-signal. Furthermore, they should be long enough to be used e.g. as enable-signal for a data-latch, discussed in previous sections about data- and address-latch submodules.

Generating clock-phases A..D from clock-edge pulses

These newly created pulses (Pr and Pf) can be divided using data-latches placed in cascade.

The outputs of each of these cascaded latches can be used to form 4 new signals, as shown here.

These signals rise one by one, and then fall one by one, in the same order.

Just like Pr and Pr, these newly created signals A, B, C and D are considered intermediate signals - they are only used to generate other signals.

For the sake of discussion, these 4 signals are called "clock-phases".

Generating phase-pulses P0..P2 from clock-phases

Using combinational logic (such as AND, OR and NOT), phase-pulses P0 to P3 can finally be created from clock-phases A to D.

(For example, phase-pulse P0 is defined as "B AND ( NOT C )", as can be seen in the figure.)

Phase-pulse P3 is not actually used to trigger subsystem-activity in the CPU, but may be implemented for debugging-purposes.

Contrary to the "artificial" length of Pr and Pf, the length of each phase-pulse is equal to exactly half the length of an input-clock pulse.

Generating a "clock good" signal CLK_EN

In order to operate the CPU, reset has to be released. The clock may or may not be already running at that point.

At any rate, there is no guarantee that, when reset is released, the clock-signal is low.

If no provisions were taken, subystems waiting for reset to be released in order to start operation, may see a falling-edge pulse Pf before Pr, or see only part of Pr or Pf.

This could cause undefined behaviour.

To prevent this, Pr and Pf are not simply emitted at every rising respectively falling edge of the clock-input, as suggested earlier.

Instead, the first Pr ("3" in the figure) is only emitted after the first falling edge ("2") after reset is released ("1"). The first Pf-pulse then follows this first Pr-pulse, then the second Pr-pulse is emitted, and so on.

Following from this, phase-pulse P0 will always be the first phase-pulse emitted after reset has been released, followed by P1, etc.