The CPU has a modular design: its implementation is spread out over a number of individual plug-in modules on an interconnecting baseboard.
The main reason for this is to allow for individual modules to be examined (e.g. on a breadboard), tested, and even re-implemented, as long as their electrical behaviour is left unchanged.
For instance, it can be entertaining to see a single logic-IC being used instead of many transistors. Using other logic-families (e.g. TTL, CMOS) becomes possible as well.
In this chapter...
(The order of subsections is more or less arbitrary - each subsection discusses an individual module. See the chapter on architecture to read more about interaction between modules.)
- During each instruction-cycle, a data-bit is read, and then inverted using a data-latch, in order to decide where in the program to proceed next. Although being a very simple module, this is essentially the "heart" of the Qibec CPU.
- Using four identical multiplexer-modules, the value of aforementioned data-bit selects between simply continuing with the next program-word, or jumping (branching) to a different location in the program.
- In order to advance to the next program-word in ROM, two identical increment-modules are combined to increment a given 16-bit address by one.
- Several identical address-latch modules are combined to form two 16-bit latches, in order to stabilise the address-bus (or program-counter) output.
- There is one timing- and control-module in the CPU, which divides the input-clock signal and handles reset-requests. This is probably the most complex module.
Although not part of the CPU itself, a RAM- & ROM-interface module, or "bridge", also exists.
This module listens on the CPU's address- and data-bus for activity, and communicates relevant data to the outside world on-the-fly, e.g. to a host-PC or mass-storage device. This module also serves as debugging-interface, and generates the CPU's clock- and reset-signals.
The RAM- & ROM-interface is not discussed here.