Data-latch module: introduction
Although actually being the "core" of the Qibec CPU, the data-latch module is very simple, and consists of only 1 logic block. An implementation of a data-latch using only NAND-gates is shown.
This section introduces logic which, contrary to logic gates discussed before, can keep a state.
Combinational vs sequential logic
The Boolean gates and functions discussed in the section about Boolean logic all belong to a class of logic called combinational logic. For such a gate, its output-values are a direct function of its input-values - it can't keep a state.
An example of a combinational logic gate is the NAND-gate.
Another class of logic exists - sequential logic - where outputs are not only dependent on inputs, but also on the input-history. Gates belonging to this class can keep a state.
An example of a sequential gate is a Set-Reset-latch - or SR-latch - discussed hereafter.
Creating an SR-latch out of NAND-gates
An SR-latch has 2 outputs, Q and Q-overline, always being each others inverse. Furthermore, it has 2 inputs, S-overline and R-overline - short for Set and Reset.
The SR-latch has 2 stable states. Its behaviour is as follows:
- in case both S-overline and R-overline are inactive, the SR-latch is idle - its outputs don't change, and maintain the state they are in
- in case only Set-input S-overline is activated, output Q is set high
- in case only Reset-input R-overline is activated, output Q is set low
It's possible to construct such a sequential gate from combinational gates such as NAND-gates.
When using NAND-gates in the configuration presented here, the SR-latch's inputs are low-active, which means the common concepts of "active" and "inactive" are swapped - a high state corresponds to inactive, and a low state corresponds to active (hence the name, and hence the overbar-symbol).
To see how this gate works, start by assuming the SR-latch is idle (both inputs inactive), and assume an arbitrary output (Q high or low). Then imagine either of the inputs (but not both at once) being activated. Then follow the wires, using the NAND-function's rules.
Creating a data-latch out of an SR-latch
The data-latch block was already introduced in the section about the CPU's subsystems, along with its functional behaviour.
Using an SR-latch and 2 NAND-gates, a data-latch can be constructed as shown here.
(The resistor between output Q and input D is not actually part of the data-latch, but is added to be able to invert the signal present at the input, as described in the section about the CPU's subsystems.)
A data-latch is sometimes called transparent latch, because when its enable-input is active, a signal applied at input D becomes immediately available at output Q, as if the gate was not there - or transparent.